Digital System Design Lab

Category

미분류

[Paper] Our paper, “Highly Utilized Merge Mode Estimation for a Hardware-based HEVC encoder” is accepted at JSPS’17.

[Paper] Our paper, “Highly Utilized Merge Mode Estimation for a Hardware-based HEVC encoder” written by Tae Sung Kim, Chae Eun Rhee, and Hyuk-Jae Lee is  accepted at JSPS’17.

[Paper] Our paper, “Fine-Scalable SPIHT Hardware Design for Frame Memory Compression in Video Codec”, is published at JSTS’17

Our paper,“Fine-Scalable SPIHT Hardware Design for Frame Memory Compression in Video Codec” written by Sunwoong Kim, Ji Hun Jang, Hyuk-Jae Lee, and Chae Eun Rhee is published at JSTS’17.

[Paper] Our paper, “Compression Efficiency Evaluation for Virtual Reality Videos depending on Projection Schemes” is published at SPC’17.

Our paper,“Compression Efficiency Evaluation for Virtual Reality Videos depending on Projection Schemes” written by Byeong Chul Kim and Chae Eun Rhee is published at SPC’17.

© 2017 Digital System Design Lab — Powered by WordPress

Theme by Anders NorenUp ↑