Digital System Design Lab

[연구생 모집] 석사과정 및 학부 연구생을 모집합니다.

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우리 랩은 꿈의 비디오 애플리케이션들을 일상 생활에서 실현 가능하게 하는 기술들을 연구하고 있습니다. 8, 12K의 UHD 비디오를 플레이할 수 있게 합니다. 거닐 수 있는 가상현실(VR) 공간을 만들어냅니다. 미래 메모리와 병렬 컴퓨팅 구조를 사용하여 실현해 냅니다.   함께 연구하고 발전하고 싶은 연구생들은 이채은… Continue Reading →

[Paper] Our paper, “Highly Utilized Merge Mode Estimation for a Hardware-based HEVC encoder” is accepted at JSPS’17.

[Paper] Our paper, “Highly Utilized Merge Mode Estimation for a Hardware-based HEVC encoder” written by Tae Sung Kim, Chae Eun Rhee, and Hyuk-Jae Lee is  accepted at JSPS’17.

[Paper] Our paper, “Fine-Scalable SPIHT Hardware Design for Frame Memory Compression in Video Codec”, is published at JSTS’17

Our paper,“Fine-Scalable SPIHT Hardware Design for Frame Memory Compression in Video Codec” written by Sunwoong Kim, Ji Hun Jang, Hyuk-Jae Lee, and Chae Eun Rhee is published at JSTS’17.

[Paper] Our paper, “Compression Efficiency Evaluation for Virtual Reality Videos depending on Projection Schemes” is published at SPC’17.

Our paper,“Compression Efficiency Evaluation for Virtual Reality Videos depending on Projection Schemes” written by Byeong Chul Kim and Chae Eun Rhee is published at SPC’17.

[News] Digital System Design Lab in CES’17

 

[News] CES’17 Poster and Brochure

[PDF] CES 2017 Poster [PDF] CES 2017 Brochure

[Paper] Our paper, “Complexity Reduction by Modified Scale-Space Construction in SIFT Generation Optimized for a Mobile GPU”, is accepted at TCSVT’16.

Our paper, “Complexity Reduction by Modified Scale-Space Construction in SIFT Generation Optimized for a Mobile GPU” written by Chulhee Lee, Chae Eun Rhee, and Hyuk-Jae Lee is accepted at TCSVT’16.  

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